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W9751G6IB
7.3.8
Self Refresh Exit Command
(CKE = "H", CS = "H" or CKE = "H", CS = "L", RAS = "H", CAS = "H", WE = "H", BA0, BA1,
A0 to A12 = Don’t Care)
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be
stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least t XSNR
must be satisfied before a valid command can be issued to the device to allow for any internal refresh
in progress. CKE must remain HIGH for the entire Self Refresh exit period t XSRD for proper operation
except for self refresh re-entry.
Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting
at least t XSNR period and issuing one refresh command (refresh period of t RFC ). NOP or Deselect
commands must be registered on each positive clock edge during the Self Refresh exit interval t XSNR .
ODT should be turned off during t XSRD .
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2
SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh
mode.
7.3.9
Refresh Command
( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don’t Care)
Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles
at an average periodic interval of t REFI (max.) .
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle)
state. A delay between the auto refresh command (REF) and the next activate command or
subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (t RFC ).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command
and the next Refresh command is 9 x t REFI .
T0
T1
T2
T3
Tm
Tn
Tn + 1
CLK/CLK
CKE
"HIGH"
≧ tRP
≧ tRFC
≧ tRFC
CMD
Precharge
NOP
NOP
REF
REF
NOP
ANY
Figure 13 — Refresh command
Publication Release Date: Oct. 23, 2009
- 22 -
Revision A06
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